The present invention relates in general to electronic signal processing, and more specifically, to digital to analog signal conversion.
A current steering digital-to-analog converter (DAC) converts a digital data stream input into a corresponding analog signal output. FIG. 1 shows a portion of a typical current steering DAC 100 in which a digital data stream is applied to a synchronous digital output latch 101. “Synchronous” means that the data on the latch input is transferred to the output in response to triggering of the latch by a clocking signal. In some applications, considerable digital processing is involved in producing such a digital data stream, but in the context of a DAC, such preceding digital circuitry need not be described. When the latch 101 is clocked, the data present on the D-input is transferred to the Q output, and its complement is transferred to the Q-bar output.
The outputs of latch 101 asynchronously control switch drivers 102, which in turn control differential switching elements 103. “Asynchronously” means that the logic state of the outputs of the switch drivers 102 and the differential switching elements 103 change state in response to their inputs changing state rather than in response to a clocking signal. For a given logic state present on the output of the latch 101, one switch of the differential switching elements 103 will be “ON,” and the other will be “OFF”. When the logic state on the output latch 101 changes, the ON-OFF states of the differential switching element 103 provide an analog signal at output terminals 106.
In theory, such a current steering DAC 100 can operate at any frequency to provide an analog output corresponding to the digital data input. In practice, errors and noise occur throughout the system, the effects of which increase with operating frequency. These effects may be code dependent and may result in harmonic distortion and harmonic spurs in the analog output signal.
A current switching DAC may employ multiple current switching elements. If each individual switching element is clocked from the same clock buffer, which may be desirable to minimize switching instant mismatch, the clock buffer may see a load dependent upon the number of elements switching. As the number of elements switching is related to the signal being processed, the clock may see a signal dependent load. Consequently, there may be a signal dependent clocking instant, resulting in third order distortion.
For example, FIG. 2 illustrates a clock driver 210 connected to switching element 240 which may be a PFET or an NFET. When clock input 205 changes state, for example from high to low, the output of the driver 210 will change from low to high, thereby turning “ON” switching element 240. Switching element 240 has inherent coupling capacitance 220 between the gate to drain and coupling capacitance 230 between gate to source. Thus, due to coupling, the clock driver 210 is dependent on the data that is on nodes 250 and 255. For example there is a difference in the current flowing into and out of the clock driver 210 when the data between node 250 and node 255 is changing and when the data is not changing. This difference in load, seen by clock driver 210, based on the data on nodes 250 and 255 introduces third order harmonic distortion, which is not desirable.
One approach to reducing code dependent noise is presented in FIG. 8 of U.S. Pat. No. 6,344,816, which describes adding an additional clocked circuit called a “dummy latch” in parallel with the output latch 101. The output of the dummy latch is not itself used in any way, rather the dummy latch and the output latch 101 are connected and operated such that with every cycle of the clocking signal, one of the latches will change state and the other will not. Thus, if the output latch 101 changes state with the data signal, the dummy latch maintains its logic state, and if the output latch 101 maintains its logic state constant with an unchanging data signal, then the dummy latch will change logic states. However, the attempt to equalize the loading to the clock by the addition of dummy latches and the corresponding support circuitry, may add to the overall complexity, overhead, mismatch, power consumption, and size of the implementation.
Thus, there is a need for an efficient system and method for a low distortion current switch, which ensures that the load seen by the clock buffer is the same in every clocking cycle, while achieving low third harmonic distortion.